The present invention relates to a disk rotation control device, and more particularly to a spindle motor drive control circuit for an optical disk, for example.
In case of that a disk on which a digital signal is recorded in a manner of a constant linear velocity (CLV) is subjected to tracking by an optical pickup, it is driven at a decreasing rotational velocity as the optical pickup moves from the inner periphery of the disk to the outer periphery thereof. The rotational velocity of the disk is controlled by controlling the rotational velocity of a spindle motor in such a manner that a synchronous clock in synchronism with a signal reproduced from the disk provides a prescribed frequency. The synchronous clock is generated from the reproduced signal by a phase lock loop circuit.
An explanation will be given of an example of a DVD device.
FIG. 10 is a block diagram of a circuit for controlling a spindle motor in the DVD device. In FIG. 10, reference numeral 1 denotes a disk; 2, an optical pickup; 3, a spindle motor; 4, a drive amplifier of the spindle motor; 5, an analog signal processing circuit for equalizing a reproduced signal; 6, a circuit for digitally processing the reproduced signal; 7, a PLL circuit; 8, a frequency comparator; 9, a phase comparator; 10, an arithmetic unit; and 11, a PWM signal generation circuit.
An explanation will be given of the operation of the DVD device. The disk 1 is activated by the drive amplifier 4. A signal reproduced is from the disk 1 and read by the optical pickup 2. The signal is wave-equalized by the analog signal processing circuit 5. The data in the reproduced signal are processed by the digital signal processing circuit 6. Then, the synchronizing signal recorded at prescribed intervals are also extracted. A channel clock (synchronous clock for data read in synchronism with the reproduced signal) is generated by the PLL (phase-locked loop) circuit 7.
The channel clock is supplied to the frequency comparator 8. On the other hand, in the DVD device, the channel clock central frequency when the disk 1 is rotated at a constant linear velocity is 26.16 MHz. The clock at this frequency is also supplied to the frequency comparator 8 as a reference clock by a quartz oscillator. In the frequency comparator 8, the channel clock extracted from the PLL circuit 7 is compared with the reference clock to provide a frequency error signal.
Like the frequency comparator 8, the phase comparator 9 is also supplied with the reference clock at 26.16 MHz. The reference clock is divided at recording intervals of the synchronizing signal (the period of the divided clock is equal to that of the synchronizing signal when the disk 1 is rotated at a constant linear velocity). The divided clock is phase-compared with the synchronizing signal to provide a phase error signal.
The frequency error signal and phase error signal are supplied to the arithmetic unit 10. They are multiplied by an integer and gain-adjusted. Further, they are added to provide an output. An error signal output from the arithmetic unit 10 is supplied to the PWM signal generation circuit 11 for its PWM(pulse wide module) conversion. The PWM converted error signal is supplied to the amplifier. The rotational velocity of the spindle motor 3 is controlled so that the amplifier can cancel the PWM error signal. Thus, the disk is rotated at a constant linear velocity.
As described above, in the DVD device, the rotation control of the spindle motor 3 is performed in a CLV system with a constant linear velocity. However, unlike the CAV system with a constant angular velocity, in a track jump, e.g. from an inner periphery to an outer periphery and vice versa other than normal reproduction, the rotation speed of the disk 1 varies greatly. Therefore, it takes a long time to establish the spindle motor in a state of a constant linear velocity again by inertia of the disk so that the signal can be read. This problem can be solved by reading the signal in the CAV system to improve access capability. However, when the DVD signal recorded in the CLV system is read (reproduced) by the CAV system, the frequency of the reproduced signal increases toward the outer periphery. The reproduced signal must be processed correspondingly at a higher speed.
The access speed of a memory used for a storage circuit in the digital signal processing circuit at a later stage has a limit. The PLL circuit must in a wide frequency band. Further, on the inner periphery, only low speed processing is permitted so that enhancement of the rotational velocity of the disk is limited.